Integrated circuits (ICs) used in a number of embedded devices such as smartcards or secure elements can contain a secret security key and carry out secret data.
Integrated circuits can be vulnerable to attacks on the physical structure of the integrated circuit device (such as a chip, semiconductor device, etc.).
Integrated circuits may include a number of protection blocks to ensure protection against attacks, such as one or more sensors which aim at detecting possible attacks. For example, Integrated Circuits may comprise sensors for detecting physical attacks, including but not limited to probing attacks or perturbation attacks, a shield, a digital sensor, etc. Integrated circuits may be configured to detect cyber-attacks, using for example CFI (Control Flow Integrity) verification.
The structure of an integrated circuit often contains certain points (referred to as Single Points Of Failure or SPOF) that correspond to critical elements of the Integrated Circuit whose failure can result in stopping the whole Integrated Circuit from operating in a secure way.
Single-Points Of Failures are design weaknesses which, if existing and subsequently localized by an attacker, can jeopardize the security of the integrated circuit.
An Integrated circuit comprises a number of sensitive functional blocks, such as protection blocks, which produce critical signals (e.g. alarms) when they detect an abnormal operation of the Integrated Circuit. If an alarm is a single signal (corresponding to one wire), then it represents a “single Point Of Failure” (SPOF). Indeed, an attacker can cut this vulnerable “wire” corresponding to the SPOF to cancel the alarm and thus gain access to all the secrets contained in the “edited” circuit as well as to the instances of the same product line sharing the same secrets, using a tool like a Focused Ion Beam (FIB). Still, circuit edition with FIB is often difficult, because nets are not easily reached by the tool (e.g. owing to routing congestion on top of it), and because the FIB is not fully reliable. Protection against FIB attacks thus usually assumes that an attacker is only able to “edit” (i.e., cut, open, or tie to ‘0’ or ‘1’) a limited number of nets.
A major challenge of secure integrated circuits is accordingly detection and elimination of single Points Of Failures in circuits. SPOFs represent the “weakest link” in the security chain of Integrated Circuits. The fact that a complex detection IP might be bypassed by a single FIB cut represents important security vulnerability. The effect of a FIB can be to open (i.e. disconnect) a net, or even to tie it to ‘0’ or ‘1’. Indeed, the FIB tool is also able to repair circuits, and in that respect, it can be used to force the value of arbitrary nets.
It is known to diversify alarms, typically by making them redundant according to the following approaches:                simple duplication (or multiplication) of the signals,        encoding of the signals so that alterations can be themselves detected,        using multiple independent tests (e.g. in a shield, different areas are checked independently).        
When manually implementing the multiplication of alarm signals, it is possible that some of them be forgotten. Or, even if it is properly implemented, it can happen that the synthesizer optimizes the diversity away. For instance, the various alarm signals can be refactored so that a new single Point Of Failure re-appears.
Existing approaches are based on Automatic Test Patterns Generation (ATPG). Such solutions have been proposed to test integrated circuits in order to identify SPOF using test vectors. For example, US patent referenced 6134689A describes a method of testing an integrated circuit containing a logic device, the method including the steps of identifying a first test vector corresponding to a test failure resulting from testing of the logic device, converting the first test vector from an input pin format into state data associated with the logic device, and searching the state data to identify a set of last shift transitions.
Other solutions are based on simulations and lie on post-productions foundry tests. However, even if IC process is realized in the cleanest and most verified industry conditions and even if some dusts and process variations are tolerated, physical errors on die can still occur, due for example to lower wafer quality on periphery, dusts during masking or patterning, wafer dicing. Such existing post-production foundry tests verify the signals continuity of the die, through scan-chain for example, according to plan tests. These plan tests are generated thanks to conventional software techniques (such as mutation testing) and only meet validation criteria (such as statement coverage, branch coverage, etc.). The plan tests mainly consist in revealing whether an input or output of a gate is stuck to an undesired level or whether a metal wire or via has been corrupted during the several fabrication phases without taking into account the pertinence of the tested signal.
There is accordingly a need to detect Points Of Failure in an IC device.